Analog circuits often need to distribute a clock signal to multiple voltage domains through the course of their operation. A common situation is in CMOS Analog-to-Digital Converters (ADCs) used in communication and video systems, where the input sampling switch is on 2.5/3.3 Volt domain and the core of the ADC is on 1.2 Volt domain. These two clock domains must be well aligned to allow high frequency operation with low sampling jitter and distortion. In fact, this misalignment is often one of the major sources of distortion on a high-speed ADC. In certain conditions, it may even be the dominant factor.
The circuit of FIG. 1 is typically used for transferring the clock signal from the 1.2 V domain (LV—Low Voltage) to 2.5 V or 3.3 V domain (HV—High Voltage). PMOS transistors (M3/M4) must be weaker than the lower NMOS (M1/M2), to ensure correct operation. One of the transitions depends on the positive feedback of the upper PMOS transistors, and so it is always slower.
In the circuit of FIG. 1, the minimum input-to-output delay is when clkLV goes low, which makes M2 push clk1HV to low. On the other transition, M1 must first push its drain voltage down, and then M4 pushes clk1HV to high, which takes more time.
As shown in FIG. 2, this effect distorts the output duty cycle (38%-47% with 1 GHz clock), thereby misaligning the output clock at HV from the original LV one.
The level converter shown in FIG. 3 operates on the complementary output, and its minimum input-to-output delay is when clkLV (and thus when clk2HV) goes high. The output duty cycle is also distorted, but in the opposite direction (56%-67% with 1 GHz clock, as shown in FIG. 4).
Several improved level converter circuits have been proposed in literature, but none addresses the fundamental asymmetry, described above, that generates transition dependent delay times.
This is a serious problem, because to align the LV clocks with the HV clocks, a delay must be added to the LV clock. For this alignment to be effective the level converter must present a similar propagation delay in the two edges—this is achieved by maintaining the duty-cycle in the LV-to-HV conversion. Furthermore, to enhance the alignment robustness across process, temperature and supply voltage variations, it is also important to minimize the propagation delay of the level converter.